Xcena Cuts Data Movement to Address Memory Bottlenecks

T2Covered by 1 source · first reported by Semiconductor Engineering / SemiWiki / EE Times / EE Journal / Electronics Weekly at 28 Sept, 07:30 UTC

Xcena’s MX1 uses CXL to push compute into memory by combining DDR5, SSDs, and RISC-V cores while easing programmability. The post Xcena Cuts Data Movement to Address Memory Bottlenecks appeared first on EE Times.

hardware

Sources

• T2Xcena Cuts Data Movement to Address Memory BottlenecksSemiconductor Engineering / SemiWiki / EE Times / EE Journal / Electronics Weekly28 Sept, 07:30