FormalOS adds structure to RTL verification and sign-off

T2Covered by 1 source · first reported by Semiconductor Engineering / SemiWiki / EE Times / EE Journal / Electronics Weekly at 02 Nov, 11:51 UTC

Lubis EDA has released FormalOs, a verification infrastructure platform which is designed to be a tool-agnostic orchestration layer for verification for SoC, asic and IP sign-off projects. According to the […] The post FormalOS adds structure to RTL verification and sign-off appeared first on…

hardwarereleases

Sources

• T2FormalOS adds structure to RTL verification and sign-offSemiconductor Engineering / SemiWiki / EE Times / EE Journal / Electronics Weekly02 Nov, 11:51