S2C Targets Faster RISC-V Bring-Up With Prototyping and AI

T2Covered by 1 source · first reported by Semiconductor Engineering / SemiWiki / EE Times / EE Journal / Electronics Weekly at 27 Oct, 13:00 UTC

S2C showcased FPGA prototyping and AI-assisted debugging at the sixth RISC-V Summit China, outlining how developers can validate complex processor designs and begin software development before first silicon. Its demonstrations connected three stages of that effort: running substantial RISC-V…

hardware

Sources

• T2S2C Targets Faster RISC-V Bring-Up With Prototyping and AISemiconductor Engineering / SemiWiki / EE Times / EE Journal / Electronics Weekly27 Oct, 13:00