How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å

T2Covered by 1 source · first reported by Semiconductor Engineering / SemiWiki / EE Times / EE Journal / Electronics Weekly at 22 Oct, 07:05 UTC

A process sequence for SRAM and logic that delivers higher performance through larger effective channel width and improved electrostatics at smaller nodes. The post How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å appeared first on Semiconductor Engineering.

hardware

Sources

• T2How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 ÅSemiconductor Engineering / SemiWiki / EE Times / EE Journal / Electronics Weekly22 Oct, 07:05