Edge AI MCU Features Multimodal Compute, Tiered Memory

T2Covered by 1 source · first reported by Semiconductor Engineering / SemiWiki / EE Times / EE Journal / Electronics Weekly at 21 Oct, 07:30 UTC

A new MCU combines AI-native acceleration with integrated high-bandwidth DRAM scalable to hundreds of megabytes. The post Edge AI MCU Features Multimodal Compute, Tiered Memory appeared first on EE Times.

hardware

Sources

• T2Edge AI MCU Features Multimodal Compute, Tiered MemorySemiconductor Engineering / SemiWiki / EE Times / EE Journal / Electronics Weekly21 Oct, 07:30