speja 0.14.6

T1Covered by 1 source · first reported by PyPI / crates.io / RubyGems / Go index / NuGet at 25 Sept, 20:03 UTC

Catch VHDL bugs before simulation: a fast Rust formatter and linter with VSG-compatible rules and configuration.

devreleases

Sources

• T1speja 0.14.6PyPI / crates.io / RubyGems / Go index / NuGet25 Sept, 20:03