Column: From 3D NAND to 3D DRAM — how vertical stacking is reshaping memory chip manufacturing

T2Covered by 1 source · first reported by JP/KR/TW: Korea Herald / Taipei Times / DigiTimes at 13 Oct, 04:06 UTC

After 2013, planar NAND flash memory began reaching its scaling limits at the 15–16nm process node. Capacitive coupling between the floating gates of adjacent memory cells increasingly disrupted their threshold voltages, making stored data harder to read reliably. The problem became…