Backside Clock Meshes Cut Skew and Power in 2nm Nanosheets (UCSC)
Researchers at the University of California, Santa Cruz published a technical paper titled “Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology.” Abstract Excerpt: “Clock meshes are used in high-performance VLSI designs to minimize skew and tolerate on-chip variation…
Sources
- T2Backside Clock Meshes Cut Skew and Power in 2nm Nanosheets (UCSC)Semiconductor Engineering / SemiWiki / EE Times / EE Journal / Electronics Weekly